Low k interconnect dielectric using surface transformation

ABSTRACT

Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.10/931,593 filed Aug. 31, 2004, which is a divisional of U.S.application Ser. No. 10/106,915 filed Mar. 25, 2002, now issued as U.S.Pat. No. 7,132,348, which applications are incorporated herein byreference in their entirety.

This application is also related to the following co-pending, commonlyassigned U.S. patent applications which are herein incorporated byreference in their entirety: “Method of Forming Buried ConductorPatterns By Surface Transformation of Empty Spaces in Solid StateMaterials,” Ser. No. 09/734,547, filed on Dec. 13, 2000; “Method ofForming Mirrors By Surface Transformation of Empty Spaces in Solid StateMaterials,” Ser. No. 09/855,532, filed on May 16, 2001; “Method ofForming Three-Dimensional Photonic Band Structures in Solid Materials,”Ser. No. 09/861,770, filed on May 22, 2001; and “Scalable HighPerformance Antifuse Structure and Process,” Ser. No. 10/106,916, filedon Mar. 25, 2002; and “Films Deposited At Glancing Incidence ForMultilevel Metallization,” Ser. No. 10/105,672, filed on Mar. 25, 2002.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits and, moreparticularly, to integrated circuit dielectrics useful for reducing thesignal delay time attributable to interconnects.

BACKGROUND OF THE INVENTION

The semiconductor industry continuously strives to reduce the size andcost of integrated circuits. One method for measuring the performance ofan integrated circuit uses the maximum clock speed at which the circuitoperates reliably, which depends on how fast transistors can be switchedand how fast signals can propagate.

One particular problem confronting the semiconductor industry is that,as integrated circuit scaling continues, the performance improvement islimited by the signal delay time attributable to interconnects in theintegrated circuit. According to one definition, integrated circuitinterconnects are three-dimensional metal lines with submicrometer crosssections surrounded by insulating material. One definition of aninterconnect delay is the product of the interconnect resistance (R) andthe parasitic capacitance (C) for the interconnect metal to the adjacentlayers. Because of the progressive scaling, the parasitic capacitance(C) has significantly increased due to closer routing of wires, and theinterconnect resistance (R) has significantly increased due to acontinuous reduction of the wire section.

The following approximations for various generations of integratedcircuit technology illustrates this problem. For example, the delay in0.7 μm technology is about 500 ps, in which about 200 ps seconds areattributable to gate delays and about 300 ps are attributable tointerconnect delays. The delay in 0.18 μm technology is about 230 ps, inwhich about 30 ps are attributable to gate delays and about 200 ps areattributable to interconnect delays. As integrated circuit scalingcontinues, it is desirable to lower the interconnect RC time constant byusing metals with a high conductivity. One high conductivity metal usedto lower the RC constant is copper. The use of copper in 0.18 μmtechnology improves the interconnect delays to about 170 ps. However,even though the delay attributable to the gates continues to decrease asscaling continues beyond the 0.18 μm technology, the overall delayincreases significantly because the interconnect delay is significantlyincreased. It has been estimated that as much as 90 percent of thesignal delay time in future integrated circuit designs may beattributable to the interconnects and only 10 percent of the signaldelay may be attributable to transistor device delays. As such, it isdesirable to lower the interconnect RC time constant by using materialswith a low dielectric constant (k).

Low-k dense materials are available having a k in a range between 2.5and 4.1. The fluorination of dielectric candidates, such as Teflon®,achieve a k of about 1.9.

Air has a k of about 1. One direction for developing low-k dielectricsincorporates air into dense materials to make them porous. Thedielectric constant of the resulting porous material is a combination ofthe dielectric constant of air (k≈1) and the dielectric constant of thedense material. As such, it is possible to lower the dielectric constantof a low-k dense material by making the dense material porous.

FIG. 1 illustrates a known Xerogel process for forming porous,silica-based material with a lower dielectric constant (k). Xerogels andAerogels based on silica incorporate a large amount of air in voids,such that dielectric constants of 1.95 and lower have been achieved withvoids that are as small as 5-10 nm. However, it is difficult to controlthe preparation of Xerogel and Aerogel low-k films. Furthermore, largeamounts of liquid solvents and non-solvents have to be removed to formthe voids, which tend to produce variability in the void size, shape anddensity, and tend to produce shrinkage that can cause high internalstress and cracking.

Therefore, there is a need in the art to provide a system and methodthat improves integrated circuit performance by reducing theinterconnect RC time constant. There is a need in the art to provide alow-k dielectric insulator for the interconnects that is easilyprepared, that is consistently formed and that does not suffer from highinternal stress and cracking.

SUMMARY OF THE INVENTION

The above mentioned problems are addressed by the present subject matterand will be understood by reading and studying the followingspecification. The present subject matter provides a low-k dielectricinsulator for integrated circuit interconnects that is easily prepared,that is consistently formed and that does not suffer from high internalstress and cracking. The low-k dielectric insulator of the presentinvention includes empty spaces formed using surface transformation. Assuch, the present invention provides a system and method that improvesintegrated circuit performance by reducing the interconnect RC timeconstant.

One aspect of the present subject matter is an integrated circuitinsulator structure. One embodiment of the structure includes a solidstructure of an insulator material, and a precisely determinedarrangement of at least one void formed within the solid structure. Theprecisely-determined arrangement of at least one void within the solidstructure lowers an effective dielectric constant of the insulatorstructure. According to one embodiment of the structure, the preciselydetermined arrangement of at least one void is formed within the solidstructure by surface transformation. According to various embodiments,the at least one void includes spherical, pipe-shaped and plate-shapedvoids.

One aspect of the present subject matter is a method of forming a low-kinsulator structure. In one embodiment, an insulator material isdeposited, and a predetermined arrangement of at least one hole isformed in a surface of the insulator material. In one embodiment, the atleast one hole includes a cylindrical hole. The insulator material isannealed such that the low-k dielectric material undergoes a surfacetransformation to transform the arrangement of at least one hole intopredetermined arrangement of at least one empty space below the surfaceof the insulator material. According to various embodiments, thepredetermined arrangement of at least one hole is formed as one or morespheres, one or more plate-shaped voids, and/or one or more pipe-shapedvoids.

One aspect of the present subject matter is a method of forming anintegrated circuit. In one embodiment, an inter-layer insulator isformed and a metal level is formed on the inter-layer insulator. Theinterlayer insulator is formed by depositing a low-k, relatively lowmelting dielectric material. A predetermined arrangement of holes isformed in a surface of the low-k dielectric material. The low-kdielectric material is annealed such that the low-k dielectric materialundergoes a surface transformation to transform the arrangement of atleast one hole into a predetermined arrangement of at least one emptyspace below the surface of the low-k dielectric material. According tovarious embodiments, the holes are formed and the material is annealedeither before or after the metal level is formed on the inter-layerinsulator.

These and other aspects, embodiments, advantages, and features willbecome apparent from the following description of the invention and thereferenced drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a known Xerogel process for forming porous,silica-based material with a lower dielectric constant (k).

FIGS. 2A-2F illustrate a portion of a silicon substrate undertaking asequence of steps for single sphere-shaped empty space formation.

FIGS. 3A-3C illustrate a portion of a silicon substrate undertaking asequence of steps for single pipe-shaped empty space formation.

FIGS. 4A-4B illustrate a portion of a silicon substrate undertaking asequence of steps for plate-shaped empty space formation.

FIG. 5 illustrates a parallel capacitor model for two distinctdielectrics in parallel with each other, the first dielectric having apermittivity of ∈₁, or a permittivity of free space (∈₀), and the seconddielectric having a permittivity of ∈₂.

FIG. 6 illustrates a series capacitor model for two distinct dielectricsin series with each other, the first dielectric having a permittivity of∈₁, or a permittivity of free space (∈₀), and the second dielectrichaving a permittivity of ∈₂.

FIG. 7 illustrates plots of k_(eff(P)) and k_(eff(S)) which are plottedas a function of the filling factor “f”, which is shown in FIGS. 5 and6, and for k₂ equal to 4.0.

FIG. 8 illustrates a transformation formed stack of empty plates with afilling factor “f” approximately equal to 0.78 and an effectivedielectric constant k_(eff) approximately equal to 1.2.

FIG. 9 illustrates metal levels for an integrated circuit.

FIG. 10 illustrates a dielectric volume, such as that bounded by themetal levels shown in FIG. 9, with a single empty sphere formed therein.

FIG. 11 illustrates a dielectric volume, such as that bounded by themetal levels shown in FIG. 9, with a close-pack structure of spheresformed therein.

FIG. 12 illustrates a dielectric volume, such as that bounded by themetal levels shown in FIG. 9, with a stack of empty plates formedtherein.

FIG. 13 illustrates the binary system {K₂O—Al₂O₃-4SiO₂} leucite-SiO₂.

FIG. 14 illustrates a phase equilibrium diagram of the ternary systemNa₂—CaO—SiO₂ showing boundary curves and tie-lines.

FIG. 15 illustrates a phase equilibrium diagram of ternary systemNa₂—CaO—SiO₂ showing isotherms.

FIG. 16 illustrates one embodiment for forming a integrated circuit.

FIG. 17 illustrates one embodiment for forming a low-k insulator fordevice isolation regions and/or inter-layer dielectrics.

FIG. 18 is a simplified block diagram of a high-level organization of anelectronic system according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description of the invention refers to theaccompanying drawings which show, by way of illustration, specificaspects and embodiments in which the invention may be practiced. In thedrawings, like numerals describe substantially similar componentsthroughout the several views. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe present invention. The following detailed description is, therefore,not to be taken in a limiting sense, and the scope of the presentinvention is defined only by the appended claims, along with the fullscope of equivalents to which such claims are entitled.

The present subject matter improves integrated circuit performance byreducing the RC time delays attributable to interconnects. The presentsubject matter provides a low-k dielectric insulator of greateruniformity and dimensional stability for advanced integrated circuits.The low-k dielectric insulator of the present invention includes emptyspaces, which reduces the effective dielectric constant (k_(eff)) of theinsulator, that are controllably formed using surface transformation.

As analyzed by Nichols et al. (F. A. Nichols et al., Trans. AIME 233,(10), p 1840, 1965) when a solid is heated to a higher temperature, asolid with a cylindrical hole that is beyond a critical length (λ_(c))becomes unstable. The cylindrical hole is transformed into one or moreempty spheres formed along the cylinder axis. The number (N) of spheresformed depends on the length (L) and radius (R_(C)) of the cylinder. Twomodels of diffusion are surface diffusion and pure volume diffusion.With respect to surface diffusion, for example, the relation between thecylinder length (L), cylinder radius (R_(C)), and number of spheres (N)is expressed by the following equation:

8.89×R _(C) ×N≦L≦8.89×R _(R)×(N+1).  (1)

Equation (1) predicts that no empty spheres will form if L<8.89×R_(C).Each empty sphere that forms has a radius (R_(S)) expressed by thefollowing equation:

R _(S)=1.88×R _(C).  (2)

If the cylinder has sufficient length L to form two spheres, thecenter-to-center spacing between the spheres corresponds to the criticallength (λ_(C)) and is provided by the equation:

λ_(C)=8.89×R _(R).  (3)

Pure volume diffusion provides similar results, with slightly differentconstants. For example, depending on the exact magnitude of thediffusion parameters, λ_(C) can vary from 9.02×R_(R) to 12.96×R_(R). Oneof ordinary skill in the art will understand that the diffusion model iscapable of being determined by experiment. The remainder of thisdisclosure assumes surface diffusion. One of ordinary skill in the artwill understand, upon reading and comprehending this disclosure, how toapply the teachings of the present invention to another diffusion model.

As analyzed by Sato et al. (T. Sato et al., VLSI Dig., p 206, 1998), adeep trench in silicon, which has a melting temperature of 1400° C., istransformed into empty spheres along the axis of the original trench ata reducing ambient of 10 Torr of hydrogen and an annealing temperatureof 1100° C. The empty spheres are uniformly sized and spaced.

As analyzed by Sato et al. (T. Sato et al., 1999 IEDM Digest, paper20.6.1), various shaped empty spaces such as spheres, pipes, and platesare capable of being formed under the surface of a silicon substrate.The shape of the empty spaces formed during the annealing conditionsdepends on the size, number and spacing of the cylindrical holes thatare initially formed at a lower temperature.

FIGS. 2A-2F illustrate a portion of a silicon substrate undertaking asequence of steps for single sphere-shaped empty space formation. Acylindrical hole 210 is formed in the surface 212 of a volume of a solidmaterial 214. As used here, the term hole refers to a void defined bythe solid material. The material 214 is heated (annealed) and undergoesthe transformation illustrated in FIGS. 2B through 2F. The result of thesurface transformation process is an empty sphere formed below thesurface 212 of the volume of material 214.

In order to form a single sphere, which holds true for forming a singlepipe or plate, the length (L) and radius (R_(C)) of the cylindricalholes are chosen such that equation (1) with N=1 is satisfied. It ispointed out that a vertical stacking of N empty spaces results if thelength of the cylindrical holes is such that equation (1) is satisfied.

In order for single surface-transformed spheres to combine with othersurface-transformed spheres, the center-to-center spacing (D_(NT))between the initial cylindrical holes will satisfy the followingequation:

2×R _(C) <D _(NT)<3.76×R _(C).  (4)

Satisfying this equation prevents the adjacent initial cylindrical holesfrom touching, yet allows the adjacent surface-transformed spheres tocombine and form pipe and plate empty spaces, as shown in FIGS. 3A-3Cand FIGS. 4A-4B and described below.

FIGS. 3A-3C illustrate a portion of a silicon substrate undertaking asequence of steps for single pipe-shaped empty space formation. A lineararray of cylindrical holes 310 is formed in a surface 312 of a solidmaterial 314. The cylindrical holes 310 have a center-to-center spacing(D_(NT)) as calculated using equation (4). The material 314 is heated(annealed) and undergoes the transformation illustrated in FIGS. 3Bthrough 3C. The result of the surface transformation process is an emptypipe-shaped void 318 formed below the surface 312 of the volume ofmaterial 314. The radius (R_(P)) of the pipe 318 is provided by thefollowing equation:

$\begin{matrix}{R_{P} = {\sqrt{\frac{8.86 \times R_{R}^{3}}{D_{NT}}}.}} & (5)\end{matrix}$

FIGS. 4A-4B illustrate a portion of a silicon substrate undertaking asequence of steps for plate-shaped empty space formation. Atwo-dimensional array of cylindrical holes 410 is formed in a surface412 of a solid material 414. The cylindrical holes 410 have acenter-to-center spacing (D_(NT)) as calculated using equation (4). Thematerial 414 is heated (annealed) and undergoes the transformationillustrated in FIG. 4B. The result of the surface transformation processis an empty plate-shaped void 420 formed below the surface 412 of thevolume of material 414. The thickness (T_(P)) of a plate 420 is given bythe following equation:

$\begin{matrix}{T_{P} = \frac{27.83 \times R_{C}^{3}}{D_{NT}^{2}}} & (6)\end{matrix}$

The present subject matter forms low-k materials using surfacetransformation. That is, the present subject matter incorporates surfacetransformation formed empty spaces to lower the effective dielectric(k_(eff)) of an insulator. The size, shape and spacing of empty spacesis controlled by the diameter, depth and spacing of cylindrical holesinitially formed in a solid dielectric material that has a definedmelting temperature. Empty spaces or voids are formed after annealingbelow the defined melting temperature. The empty spaces or voids arecapable of being formed with a spherical, pipe, or plate shape, orcombinations of these shapes.

The surface transformed empty spaces do not provide additional stress orproduce a tendency to crack because the volume of air incorporated inthe surface transformed empty spaces is equal to the volume of airwithin the initial starting pattern of cylindrical holes. It is notedthat if the cylinder length (L) is equal to an integer of a criticallength (λ_(c)) such as 1×λ_(c) to form one sphere, 2×λ_(c) to form twospheres, 3×λ_(c) to form three spheres, etc., then the surface will besmooth after the surface transformed empty spaces are formed. However,if the cylinder length (L) is not equal to an integer of a criticallength (λ_(c)), then the surface will have dimples caused by air in thecylinder attributable to the length beyond an integer of a criticallength (λ_(c)). That is, for a given length L and λ_(c), the number ofspheres formed is the integer of L/λ_(c), and the remainder of L/λ_(c)contributes to the dimples on the surface.

FIG. 5 illustrates a parallel capacitor model for two distinctdielectrics in parallel with each other, the first dielectric having apermittivity of ∈₁, or a permittivity of free space (∈₀), and the seconddielectric having a permittivity of ∈₂. The capacitor 522 has a firstelectrode 524 and a second electrode 526. The first electrode 524 andthe second electrode 526 both have a length (A) and are separated by adistance (d). A first dielectric 528 is formed between the first andsecond electrodes, and a second dielectric 530 is formed between thefirst and second electrodes and parallel to the first dielectric. Thefirst dielectric extends a distance A₁, which is a fraction of thelength A, from one end of the electrodes as provided by the followingequation:

A ₁ =f×A.  (7)

The variable f represents the fraction (or filling factor) of the firstdielectric 528, which is air (k≈1) in one embodiment. The seconddielectric 530 extends a distance A₂, which is a fraction of the lengthA, from the opposing end of the electrodes as provided by the followingequation:

A ₂ =A−A ₁=(1−f)×A.  (8)

The effective dielectric constant (k_(eff(P))) for the parallelcapacitor model is represented by the following equation:

k _(eff(P)) =f+k ₂×(1−f).  (9)

FIG. 6 illustrates a series capacitor model for two distinct dielectricsin series with each other, the first dielectric having a permittivity of∈₁, or a permittivity of free space (∈₀), and the second dielectrichaving a permittivity of ∈₂. The capacitor 622 has a first electrode 624and a second electrode 626. The first electrode 624 and the secondelectrode 626 both have a length (A) and are separated by a distance(d). A first dielectric 628 is formed in series with a second dielectric630 between the first and second electrodes. The first dielectric 628has a width d₁, which is a fraction of the distance d as represented bythe following equation:

d ₁ =f×d.  (10)

The variable f represents the fraction (or filling factor) of the firstdielectric 628, which is air (k≈1) in one embodiment. The seconddielectric has a width d₂, which is fraction of the distance d asrepresented by the following equation:

d ₂ =d−d ₁=(1−f)×d.  (11)

The effective dielectric constant (k_(eff(S))) for the series capacitormodel is represented by the following equation:

$\begin{matrix}{k_{{eff}{(S)}} = {\frac{1}{f + {( {1 - f} ) \times \frac{1}{k_{2}}}}.}} & (12)\end{matrix}$

FIG. 7 illustrates plots of k_(eff(P)) and k_(eff(S)) which are eachplotted as a function of the filling factor variable “f” and for k₂equal to 4.0. One of ordinary skill in the art will recognize thatsimilar plots can be made for other dielectric constant values. Theeffective dielectric constant (k_(eff)) of a material of dielectricconstant k₂ with embedded empty spaces depends on the detailed size,shape orientation and spacing of the empty spaces relative to a set ofparallel electrodes. However, the k_(eff) for the material with adielectric constant k₂ with embedded empty spaces is bounded between theeffective capacitance for the parallel capacitor model (k_(eff(P))) andthe effective capacitance of the series capacitor model (k_(eff(S))).

FIG. 8 illustrates a transformation formed stack of empty plates with afilling factor “f” approximately equal to 0.78 and an effectivedielectric constant k_(eff) approximately equal to 1.2. This figureillustrates one example of the effective dielectric constant (k_(eff))for a dielectric film of SiO₂, which has a dielectric constant (k) of4.34 and a melting temperature of 1610° C., that incorporates surfacetransformation formed empty spaces. In the illustrated example, thesurface transformation produces a vertical stack of empty plates in thedielectric film between the electrodes 624 and 626. The number of emptyplates formed depends on the length of the cylindrical holes.

From equation (6), it is determined that the thickness T_(P) of theempty plate has a maximum value of 6.95×R_(C) when D_(NT) is near theminimum allowed value of 2×R_(C) as inferred from equation (4). Fromequation (3), the center-to-center spacing (λ) of empty plates is8.89×R_(C). It can be calculated that f≈0.78. The expression ofk_(eff)(s) applies and results in k_(eff)=1.2 for k₂=4.34 and f=0.78.

FIG. 9 illustrates metal levels for an integrated circuit. The figureillustrates a first metal level 940, a second metal level 942, and athird metal level 944. The metal levels lie in approximately parallelplanes. Individual lines within the metal levels typically run eitherparallel to or orthogonally to individual lines in other metal levels.The metal levels are separated by inter-layer dielectrics (not shown).The metal levels form boundaries for dielectric regions, or volumes,between the individual lines and the metal levels. For simplicity, thedielectric volumes are illustrated as a rectilinear volume in FIGS. 10through 12. A goal is to maximize the amount of air that is incorporatedinto these dielectric volumes using surface transformation formed emptyspaces.

FIG. 10 illustrates a dielectric volume 1014, such as that bounded bythe metal levels shown in FIG. 9, with a single empty sphere 1010 formedtherein. The dielectric volume often will have various shapes and sizes.As such, smaller spheres are used to obtain a larger filling factor whenthe empty spheres are packed or arranged with other spheres.

FIG. 11 illustrates a dielectric volume 1114, such as that bounded bythe metal levels shown in FIG. 9, with a close-pack structure of spheres1110 formed therein. The spheres 1110 illustrated in FIG. 11 are smallerthan the spheres 1010 illustrated in FIG. 10, and as such are capable ofbeing packed into a variety of dielectric volumes.

FIG. 12 illustrates a dielectric volume, such as that bounded by themetal levels shown in FIG. 9, with a stack of empty plates formedtherein. This figure illustrates that other shapes of surfacetransformation formed empty spaces are capable of being used to lowerthe effective dielectric constant (k_(eff)) of the dielectric volume.One of ordinary skill in the art will appreciate that various shapes andsizes of voids are capable of being used to pack various shapes andsizes of dielectric volumes.

In the example above, SiO₂ (quartz), which has a melting point of 1610°C., is used as the bulk dielectric material. For process compatibilityreasons it may be desirable or necessary to employ other solid materialsnotably with lower melting temperature (and preferably lower dielectricconstant). That is, the solid materials used should be capable of beingannealed at a temperature that does not unduly interfere or compromiseexisting integrated circuit structures.

SiO₂ has been widely used in microelectronics technology as aninter-layer dielectric, as trench isolation and as passivation betweenactive silicon device regions and interconnects. In microelectronicstechnology, metal contacts, via and interconnects are fabricated afterdevice processing in silicon, while device isolation regions arefabricated prior to device processing. The processing temperature forcontacts and interconnects is required to be low enough not tosignificantly alter impurity profiles in silicon. Corresponding thermalbudgets allowed must be below 1000° C. for time periods less than aminute, with appropriate compatibility with interconnect metallurgy. Anexample of such an SiO₂-based dielectric is the {K₂O—Al₂O₃-4SiO₂}leucite-SiO₂ binary system.

FIG. 13 illustrates the binary system K₂O—Al₂O₃-4SiO₂ (leucite)-SiO₂.FIG. 13 shows a phase diagram and associated low temperature eutectic at˜55% SiO₂ concentration. In one embodiment, such a dielectric issputter-deposited with Tungsten metallurgy as studs and as first andsecond levels of interconnects. In one embodiment, the dielectric isapplied earlier in the process for device isolation. In theseapplications, the electric deposition is followed by the creation of anappropriate array of cylindrical holes into the dielectric. Thesecylindrical holes are transformed to an empty space, such as emptyspheres, pipes or plates through an annealing process.

One embodiment uses laser pulse annealing to an appropriate temperatureclose to the melting point of the dielectric, thus achieving a desiredempty space filling factor (porosity) and low k value. In variousembodiments, tungsten interconnect technology is employed by standarddamascene or metal inlaid process.

Creating voids in an isolation regions reduces parasitic inter-diffusioncapacitance and lateral noise propagation within silicon as well asparasitic line to substrate capacitance. Creating voids within theinter-layer dielectric reduces parasitic gate-to-diffusion,line-to-diffusion and substrate capacitance components as well asinter-level and intra-level line to line capacitance. Benefits inmicroelectronic chip design include: parasitic bitline capacitancereduction; sense-amp signal improvement in array designs, such as DRAM,SRAM, NVRAM and the like; improved random logic cell designs that resultin improved density speed and power; and improved analog and digitaldesign integration within the chip by reducing noise propagation.

FIG. 14 illustrates a phase equilibrium diagram of the ternary systemNa₂—CaO—SiO₂ showing boundary curves and tie-lines. FIG. 15 illustratesa phase equilibrium diagram of ternary system Na₂—CaO—SiO₂ showingisotherms. In one embodiment, the dielectric is a multi-componentNa₂O—CaO—SiO₂ glass. In one embodiment, the dielectric is a ternaryeutectic composition of the glass. The lowest-melting eutectic of soda(Na₂O) and silica (SiO₂) is at 793° C. and of soda, lime and silica isat 725° C. These are shown in the ternary diagrams of FIGS. 14 and 15.In choosing a glass composition several factors are considered. Onefactor is whether the glass forms a suitable insulator. Another factoris whether the composition is stable during the formation of the emptyspaces. As such, it is desirable to use glass compositions which arethermodynamically invariant.

In one embodiment, the dielectric includes organic polymers such aspolytetrafluoroethylene (Teflon®). Another method for producing porouspolymers for integrated circuit applications is discussed by Farrar inU.S. Pat. No. 6,077,792 entitled “Method of Forming Foamed PolymericMaterial for an Integrated Circuit.” In one embodiment, the dielectricincludes lead acetate with a melting point of 280° C. and a dielectricconstant (k) of 2.6.

The figures presented and described in detail above are similarly usefulin describing the method aspects of the present subject matter. Themethods described below are nonexclusive as other methods may beunderstood from the specification and the figures described above. Oneaspect provides a method for forming a wide variety of insulators insemiconductor applications, such as interconnect dielectrics, and otherapplications that require or desire an insulator with a low dielectricconstant.

FIG. 16 illustrates one embodiment for forming a integrated circuit.According to this embodiment, device isolation regions are formed at1610, and one or more devices are formed at 1612. An inter-layerdielectric over the devices is formed at 1614. At 1616, a metal level isformed over the inter-layer dielectric and is appropriately connected orcoupled to the devices. One method for depositing a metal pattern is thedual damascene process. Other methods includes the single damascene orsubtractive etch metal process. It is determined at 1618 whether anothermetal level is to be formed. If it is determined that another metallevel is to be formed, then the process returns to 1614 to form anotherinter-layer dielectric and to form a metal level over the dielectric at1616 with the appropriate connections to the devices. If it isdetermined at 1618 that another metal level is not to be formed, thenthe process terminates. This process can be forming another inter-layerdielectric and forming another metal level can be repeated as many timesas necessary to produce the required number of metal levels. It is notedthat the dielectric material is chosen that has an appropriate annealingtemperature to perform the surface transformation process withoutdamaging other parts of the integrated circuit. Different dielectricmaterials are capable of being used in different parts of the integratedcircuit, as desired or required by the application.

FIG. 17 illustrates one embodiment for forming a low-k insulator fordevice isolation regions and/or inter-layer dielectrics, shownpreviously at 1610 and 1614 in FIG. 16. According to one embodiment, alow-k dielectric is deposited at 1720. Holes are formed in the low-kdielectric at 1722. At 1724, the low-k dielectric material is annealedto cause surface transformation. The result of the surfacetransformation is that the holes that were previously formed in thelow-k dielectric are transformed into empty spaces under the surface ofthe dielectric. These empty spaces lower the effective dielectricconstant. Furthermore, the use of the surface transformation techniqueallows the spaces to be arranged in such a manner as to maximize theamount of void space in the dielectric to minimize the effectivedielectric constant.

It is noted that the formation of the holes in the dielectric, asrepresented by element 1722, and/or the annealing of the dielectric, asrepresented by the element 1724, can be performed either before or afterthe metal level is formed on the low-k dielectric. For example, uponcompletion of the metal level, an appropriate resist layer is appliedand imaged with a series of holes where the hole diameter is at leastone half or less of the line to line spacing. Again, a goal is to packas much air in the dielectric volume because increasing the fillingfactor (f) of air decreases the effective dielectric constant (k_(eff))of the dielectric volume. In one embodiment of the present invention,the diameter of the voids within the dielectric volume ranges from 1micron to 0.2 micron.

It is possible to define the pattern using direct write e-beamlithography, but this is an expensive and time consuming process. Adense pattern of holes is all that is required to reduce the dielectricconstant and the associated capacitive loading effects. Varioustechniques are available to form the holes in the solid material. Onetechnique is imprint lithography. It may be desired to imprint the masktwice with an random offset of the mask between the printings in orderto achieve a high density of holes. Another technique is to form astencil using a method described by Asoh et al. (H. Asoh et al.,“Fabrication of Ideally Ordered Anodic Porous Alumina with 3 nm HolePeriodicity Using Sulfuric Acid”, J. Vac. Technol., B 19(2), Mar./Apr.2001, pp. 569-572) by first producing a metal mask that can be usedrepeatedly.

Continuing with the example, once the insulator has been patterned andholes are etched, the surface is heated rapidly to a temperature nearthe melting point of the insulator and the surface transformation ofcylindrical holes to buried empty spaces takes place. The heating isaccomplished by using a pulsed incoherent light or laser source that isapplied for a few microseconds to a few milliseconds, thereby onlyheating the uppermost layer of the wafer. The wafer is rapidly cooledafter the heat source is extinguished by the large thermal mass of thewafer.

FIG. 18 is a simplified block diagram of a high-level organization of anelectronic system according to the teachings of the present invention.The electronic system 1800 has functional elements, including aprocessor or arithmetic/logic unit (ALU) 1802, a control unit 1804, amemory device unit 1806 and an input/output (I/O) device 1808. Generallysuch an electronic system 1800 will have a native set of instructionsthat specify operations to be performed on data by the processor 1802and other interactions between the processor 1802, the memory deviceunit 1806 and the I/O devices 1808. The control unit 1804 coordinatesall operations of the processor 1802, the memory device 1806 and the I/Odevices 1808 by continuously cycling through a set of operations thatcause instructions to be fetched from the memory device 1806 andexecuted. The processor 1802 and memory device 1804, for example, areformed as integrated circuits with a low-k dielectric material accordingto the teachings of the present invention, thus lowering the RC timedelay and improving the performance of the integrated circuits and theoverall electronic system.

CONCLUSION

The present subject matter improves integrated circuit performance byreducing the RC time constant of interconnects. The present subjectmatter provides a low-k dielectric insulator of greater uniformity anddimensional stability for advanced integrated circuits. The low-kdielectric insulator of the present invention includes empty spacescontrollably formed using surface transformation. Forming low dielectricconstant materials by incorporating surface transformation formed emptyspaces enables greater control of low-k dielectric properties whileavoiding stress and cracking problems which are found in Xerogels andAerogels.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A structure, comprising: an insulator structure of an insulatormaterial; and the insulator structure including an arrangement of aplurality of voids having a predetermined void-to-void spacing, whereineach void has a shape and size formed through a surface transformationprocess, wherein the surface transformation process includes: formingholes with predetermined dimensions and spacing through a surface of theinsulator structure; and annealing the insulator structure to transformthe holes through the surface of the insulator structure into thearrangement of the voids with the predetermined void-to-void spacing,wherein the void-to-void spacing and the shape and size of each void iscontrolled by the predetermined dimensions and spacing of the holes,wherein the arrangement of at least one void within the insulatorstructure lowers an effective dielectric constant of the insulatorstructure.
 2. The structure of claim 1, wherein the insulator materialis a low-k insulator material.
 3. The structure of claim 2, wherein theinsulator material includes silicon.
 4. The structure of claim 2,wherein the insulator material includes a multi-component composition.5. The structure of claim 2, wherein the insulator material includes aeutectic multi-component composition.
 6. The structure of claim 1,wherein the insulator material has a low annealing temperature.
 7. Thestructure of claim 6, wherein the insulator material includes leadacetate.
 8. The structure of claim 6, wherein the insulator materialincludes a eutectic multi-component composition.
 9. The structure ofclaim 1, wherein the plurality of voids includes a plate-shaped void.10. The structure of claim 9, wherein the plurality of voids includes astack of a plate-shaped voids.
 11. The structure of claim 1, wherein theplurality of voids includes at least one pipe-shaped void.
 12. Astructure, comprising: an insulator structure of a low-k insulatormaterial; and the insulator structure including an arrangement of aplurality of sphere-shaped voids having a predetermined void-to-voidspacing, wherein each void has a shape and size formed through a surfacetransformation process, wherein the surface transformation processincludes: forming holes with predetermined dimensions and spacingthrough a surface of the insulator structure; and annealing theinsulator structure to transform the holes through the surface of theinsulator structure into the arrangement of the voids with thepredetermined void-to-void spacing, wherein the void-to-void spacing andthe shape and size of each void is controlled by the predetermineddimensions and spacing of the holes, wherein the precisely-determinedarrangement of at least one void within the solid structure lowers aneffective dielectric constant of the insulator structure.
 13. Thestructure of claim 12, wherein the arrangement of the plurality ofsphere-shaped voids includes a close-packed structure of empty spheres.14. The structure of claim 12, wherein at least one of the plurality ofsphere-shaped voids has a diameter of approximately 1 micron.
 15. Thestructure of claim 12, wherein at least one of the plurality ofsphere-shaped voids has a diameter of approximately 0.2 micron.
 16. Anelectronic system, comprising: a processor; and a memory coupled to theprocessor, wherein the processor and the memory are formed as at leastone integrated circuit, including: a plurality of devices; at least onemetal level operatively coupled to the plurality of devices; and aninsulator structure of an insulator material between the plurality ofdevices and the at least one metal level, the insulator structureincluding an arrangement of a plurality of voids having a predeterminedvoid-to-void spacing, wherein each void has a shape and size formedthrough a surface transformation process, wherein the surfacetransformation process includes: forming holes with predetermineddimensions and spacing through a surface of the insulator structure; andannealing the insulator structure to transform the holes through thesurface of the insulator structure into the arrangement of the voidswith the predetermined void-to-void spacing, wherein the void-to-voidspacing and the shape and size of each void is controlled by thepredetermined dimensions and spacing of the holes, wherein thearrangement of the plurality of voids within the insulator structurelowers an effective dielectric constant of the insulator structure andimproves the performance of the processor and the memory.
 17. Theelectronic system of claim 16, wherein the insulator material is a low-kinsulator material.
 18. The electronic system of claim 17, wherein theinsulator material includes silicon.
 19. The electronic system of claim17, wherein the insulator material includes a multi-componentcomposition.
 20. The electronic system of claim 16, wherein theinsulator material includes a eutectic multi-component composition. 21.The electronic system of claim 16, wherein the insulator materialincludes a material having a low melting temperature such that theinsulator material is capable of being annealed at a low annealingtemperature.
 22. The electronic system of claim 16, wherein thearrangement of the plurality of voids includes a close-packed structure.